Marvell近期热招职位来袭!

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来源: 集微网   发布者:集微网
热度83票   时间:2016年12月07日 17:18
Marvell近期热招职位列表:
Senior Firmware Manager_Shanghai
Senior Firmware Engineer_Shanghai, Chengdu
Senior SSD FAE_Shenzhen, Beijing
Physical Design Engineer_Shanghai, Chengdu

以上工程师岗位招聘多人,简历投递jiangrr@marvell.com。详细职位描述见下文
提供有竞争力的薪资福利,公司和团队氛围非常好,对于一心提升技术的人来说一定让几年之后的你更具有竞争力。

Title: Senior Manager, Firmware 
Working Location: Shanghai

Marvell is building the Firmware team in the SSD product development team. As a Senior Manager, Firmware, you will be responsible for managing a team responsible for design, implementation, verification and customer support. You will be contributing in one or more of the following domains: PCIe/NVMe/SATA, NAND, Caching, Performance, FTL, Infrastructure, Manufacturing. 
We are an ambitious team within a multi-site, multi-cultural company. Marvell develops challenging products and a unique high tech environment that encourages continued learning and growth. As a manager of this team, you will interact with different teams such as SoC design, SoC validation, SQA, Field Application Engineers and customers. We are in an Agile development process. 
Strong software engineering background (MSc or BSc in Software Engineering / Computer Science or equivalent through experience)
Minimum 12 years of relevant experience with a progression of leadership
Minimum 5 years of management experience leading a team
Thorough knowledge of C language
Successfully delivered final products
Willingness to travel (enter % of time)
Good communication skills in English
Hands-on experience with OO programming and its concepts
Experience with or passionate to learn embedded firmware
Preferred Experience:
Affinity with Agile development
Knowledge on configuration management
Knowledge on processor architectures, specifically ARM
Knowledge on NAND technology
Experience with design for and support for mass production
Affinity with electrical engineering

Title: Senior Firmware Engineer
Working Location: Shanghai, Chengdu

Marvell is building the Firmware team in the SSD product development team. As a Senior Firmware Engineer, you will be responsible for design, implementation, verification and customer support. You will be contributing in one or more of the following domains: PCIe/NVMe/SATA, NAND, Caching, Performance, FTL, Infrastructure, Manufacturing. 
We are an ambitious team within a multi-site, multi-cultural company. Marvell develops challenging products and a unique high tech environment that encourages continued learning and growth. As a member of this team, you will interact with different teams such as SoC design, SoC validation, SQA, Field Application Engineers and customers. We are in an Agile development process. 
Minimum Qualifications:
Strong software engineering background (MSc or BSc in Software Engineering / Computer Science or equivalent through experience)
Minimum 5 years of relevant experience
Thorough knowledge of C language
Hands-on experience with OO programming and its concepts
Experience with or passionate to learn embedded firmware
Willingness to travel (enter % of time)
Good communication skills in English
Preferred Experience:
Affinity with Agile development
Knowledge on configuration management
Knowledge on processor architectures, specifically ARM
Knowledge on NAND technology
Experience with design for and support for mass production
Affinity with electrical engineering

Title: Senior SSD FAE
Expected location: Shenzhen (preferred)/Beiijing

Job Description:  We are targeting to hire one talent work as FAE (field application engineer) for SSD controller product line, this job is responsible for winning designs and assist  account managers on technical level. Provides technical field design support. Qualifies design activity at the customer engineering level. Acts as a primary technical interface between the customer and the company technical support team. Develops code for use in the customer drive application.
Qualifications : Previous FAE/firmware engineer background with 5+ years experience in HDD/SSD drive vendors or controller vendors is preferred. Good team player with strong technical background as listed in required skill part. Self-motivate and can work under stress to chase opportunity win. Good communication skills and can use English as working language fluently.
Required skills:
Understanding of Embedded System Design and Firmware Development.
Serial ATA Interface and PHY.
PCIe interface. NVMe.  eMMC.
NAND technology and interfaces.
Direct customer management experience
Knowledge of SSD system requirements, customers, operation, and hands-on PC, MAC or server systems debug skills.
Understanding of key HW and SW trends within the Client or Server industry including form factors, power, performance, software applications preferred.
General knowledge about ASIC design and manufacturing flow.

Responsibility: FAE will assist the customer to understand and use Marvell storage devices in their products; with the goal to ultimately ensures successful production of customer drives using Marvell products. Typical activities include the following:
Onsite customer support.
Teach customers usage of Marvell SSD controllers.
Help customer review/debug firmware to support Marvell SSD controllers.
Support customer meetings and manage closure of action items.
Become the central liaison between customer and Marvell design team: clearly understand and explain customer issues and requests to Marvell support team.
Debug issues on the bench or customer site for host/drive compatibility issues.
Create problem report and present to customers.
Collect feature requests from customers to design team to improve product.
Competitive analysis.
Conducting tests and documenting results as required

Title: Physical Design Engineer
Working Location: Shanghai, Chengdu

Description
Implementing from Synthesis to GDSII that includes synthesis/DFT implement and check/P&R/ timing signoff and physical signoff
Cooperate with colleagues on power fixing based on power analysis result
Develop methodologies to make daily work more efficient
Cooperate with designers on RTL issues which relative to backend timing closure and congestion solve.
Debugging the flow and completion it.
 
Qualifications
BS/MS+ in EE/CS required 
Have DRC/LVS/ERC/Antenna debugging skills 
Knows Synopsys /Cadence place-and-route tool set and physical design project implementation. 
Good programming skill. 
Capable of writing Tcl or Perl. 
Familiar with synthesis, static timing analysis is an advantage.
Familiar with RTL Design in Verilog is an advantage..
Self-motivated team worker, good verbal and written communication skills in English.
Two years relative work experiences are preferred.


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